In order to achieve high product yields in mass production of integrated circuit (IC) chips, chip layout designers are often required to follow certain design rules (DRs) from chip foundries in designing chip layouts. The design rules include conditions of intersection of wires, minimum metal line width, and minimum extension of polysilicon over field, etc.
There are a set of design rules to follow when designing a layout of an IC chip, and there are various patterns in the layout. Thus, errors may inevitably exist in the patterns designed by a layout design software or may be caused by a layout designer due to the designer's mistakes. Therefore, after a layout is finished, inspections should be conducted on the patterns in the layout designed according to the design rules prior to actual manufacturing of the IC chip, which is called design rule check (DRC), an inspection process to determines whether a particular design layout conforms with the DRs. During DRC, a plurality of violations, results not complying with the design rule, corresponding to patterns may be found.
However, not all of the violations found need to be corrected. The violation patterns corresponding to the violations should be analyzed according to actual fabrication processes of the foundry to further determine whether the patterns corresponding to the violations contain those patterns that cannot satisfy layout design requirements of the foundry. Only after those unsatisfied patterns are determined and corrected by the designers, the IC chip design can enter the fabrication processes. Thus, DRC is a process ensuring that the DRs are met by the IC chip layout.
However, with the rapid development of ultra large scale integration (ULSI) circuits, the complexity of chip layout increases, and so does circuit design. Thus, the chip foundries often use more restricted rules for the design process as well as more complex design rules, which dramatically increase the amount of DR violations. Even for a single design rule, tens of thousands or even tens of millions of violations may be found after the DRC. But not all violations need to be corrected. For example, for one thousand violations found according to a particular design rule, 999 of them may be negligible according to production experiences and do not have to be corrected. However, the remaining one violation may have to be corrected by changing the corresponding pattern of the chip layout, otherwise the chip product would have quality problems.
Conventionally, the chip layout and the design rules are relatively simple, and the number of violations obtained under DRC is relatively small. Thus, the violations can be inspected one by one manually. Unfortunately, in the current semiconductor manufacturing industry, the level of inspection of the DRC still stays at the conventional level. If tens of millions of violations are found, only a portion of the violations are inspected according to a random sampling inspection method. For example, 50 out of 1000 violations may be randomly sampled and inspected at a sampling rate of 5%. Although the random sampling inspection method may save inspection time, chances are up to 95% that violations which actually need to be corrected will not be found. The problems in the layouts may only be found when a poor product yield arises. At that time, correcting the layout and manufacturing redesigned chips may dramatically increase production cost and prolong the time period of products to market, which causes huge and imponderable losses to the chip foundries.
Therefore, it is desired to provide a method to conduct an accurate and quick analysis on the violations to determine whether patterns corresponding to the violations meet the design requirements of chip foundries, and to correct patterns which do not meet the design requirements, so that successful mass production of chips with high yield may be achieved.